1. Field of the Invention
The present invention relates to the field of random-access memories (RAM) utilizing integrated circuitry. More particularly, the present invention relates to large, high density, random access memories utilizing a single device per storage cell.
2. Description of the Prior Art
Random access memories using a single device per bit, based on the use of a metal oxide silicon field effect transistor, are well known to the art. Informational charge increments are transferred between the capacitance of an addressed memory cell or storage device to the bit line capacitance. Reading, writing and refreshing is performed by conventional means. The array of memory devices is typically organized as a two dimensional matrix of rows and columns. Each row is coupled to the gates of the integrated circuit's MOSFETs which comprise that row. In the same manner, each column is coupled to the source regions of the MOSFETs which comprise that column. The drains in turn of each of the devices is usually capacitively coupled to ground. In some prior art, a merged sense line and source region serves as the columns of the array. A diffusion region is then provided for the drain of each device and is extended to form one of the capacitor plates disposed within the semiconductor surface. Alternatively, the diffusion region may be coupled to appropriate metallization to form one of the capacitor plates disposed above a corresponding capacitive diffusion region in the semiconductor substrate. See, U.S. Pat. No. 3,387,286 (1968). The performance of the storage device depends in large part on the ratio of the capacitance of the storage device to the capacitance of the sense or bit line. In order to maximize this ratio, the prior art has devised various means to increase the capacitance of the device. For example, this ratio has been increased by using the capacitance between an isolated diffusion region and the grounded substrate in which the diffusion region is formed. The capacitance of such an isolated diffusion region may also be increased by disposing a grounded, conductive line insulatively spaced above the isolated diffusion region. See U.S. Pat. No. 3,387,286 (1968).
Both of the above mentioned prior art means for providing a large cell capacitance to bit line capacitance ratio require relatively large amounts of chip area. To offset this, in the prior art the storage devices are grouped in pairs and cross connected, that is the grounded capacitive plate of a first device is coupled to the gate of a second device which is always maintained in the complementary state. Thus, a fixed potential line may be eliminated without decreasing the ratio of cell capacitance to line capacitance.
However, in each of the prior art devices discussed above as the overall cell size is decreased, the ratio of cell capacitance to bit line capacitance also significantly decreases. Therefore, the overall minimum size of each memory cell was limited by the minimum acceptable memory cell capacitance ratio.
For other relevant prior art see IBM Technical Disclosure Bulletin Vol. 15, No. 6, November 1972.